1. Field of the Invention
The present invention relates to a parallel memory device for image processing utilizing a linear transformation, and more particularly to a parallel memory device capable of processing a large quantity of image data at a high rate and achieving a high efficiency for a realization of hardware.
2. Description of the Prior Art
Generally, a parallel memory device is a memory device adapted to obtain a highly parallel characteristic by appropriately distributing, in a plurality of memory modules, data about a specific matter, which data is known in terms of the access form.
In particular, a parallel memory device for image processing is a memory device adapted to utilize the characteristic that most computations are simultaneously accessible, in various access forms, to a set of image points having a certain geometrical form such as a horizontal line, a vertical line or a block, indtead of the computations being accessible in the unit of a single image point.
In order to construct such a parallel memory device achieving simultaneous access, in various access forms, to image points taking a certain geometrical form, column rotation methods and linear transformation methods both adapted to appropriately arranged memory modules, have been used.
In accordance with the column rotation method, memory modules are arranged on the basis of a value derived by multiplying coordinates of a data matrix by appropriate constants, respectively, adding together values resulting from the multiplication, and then executing a modulo computation, by the number of memory modules, for a value resulting from the addition. For arranging the memory modules so as to enable simultaneous access in various access forms used in image processing, it is required that the number of memory modules is a prime number larger than the number of simultaneously accessible memory modules. To this end, the modulo computation by the prime number should be incorporated in an address computation circuit hardware. As a result, the circuit becomes complex and requires a long data processing time. Consequently, a degradation in the efficiency occurs in real circuits.
In accordance with the linear transformation method, memory modules are arranged on the basis of a value derived by multiplying coordinates of a data matrix, taken in the form of binary vectors, by an appropriate binary transformation matrix and XORing a value resulting from the multiplication. Since all computations are executed using only bit-unit computations such as XOR or AND, the linear transformation method has an advantage of being realizable in a simple address computation circuit, as compared to the column rotation method. In this linear transformation method, however, access in the form of horizontal line, vertical line or two-dimensional block at an optional position is impossible because the method is realized under an assumption that the number of simultaneously accessible image points is the same as the number of memory modules. In other words, this method has a limitation that simultaneous access can be possible for an image point disposed at a specific position.